SwePub
Tyck till om SwePub Sök här!
Sök i SwePub databas

  Extended search

Träfflista för sökning "WFRF:(Larsson Lars) ;pers:(Larsson Edefors Per 1967);pers:(Do Minh Quang 1969)"

Search: WFRF:(Larsson Lars) > Larsson Edefors Per 1967 > Do Minh Quang 1969

  • Result 1-6 of 6
Sort/group result
   
EnumerationReferenceCoverFind
1.
  •  
2.
  • Do, Minh Quang, 1969, et al. (author)
  • Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
  • 2007
  • In: 8th International Symposium on Quality Electronic Design (ISQED’07). ; , s. 185 - 191
  • Conference paper (peer-reviewed)abstract
    • We propose a methodology and power models for an accuratehigh-level power estimation of physically partitionedand power-gated SRAM arrays. The models offer accurateestimation of both dynamic and leakage power, includingthe power dissipation due to emerging leakage mechanismssuch as gate oxide tunneling, for partitioned arrays that deploydata-retaining sleep techniques for leakage reduction.Using the proposed methodology, dynamic, leakage and totalpower of partitioned SRAM arrays can be estimated witha 97% accuracy in comparison to the power obtained byrunning full circuit-level simulations.
  •  
3.
  •  
4.
  •  
5.
  •  
6.
  • Do, Minh Quang, 1969, et al. (author)
  • Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
  • 2004
  • In: Lecture Notes in Computer Science (LNCS) , Springer Verlag. - Berlin, Heidelberg : Springer Berlin Heidelberg. ; 3254:1, s. 869-878
  • Conference paper (peer-reviewed)abstract
    • In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables ofpower values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.
  •  
Skapa referenser, mejla, bekava och länka
  • Result 1-6 of 6
Type of publication
conference paper (6)
Type of content
peer-reviewed (4)
other academic/artistic (2)
Author/Editor
Bengtsson, Lars, 195 ... (6)
Larsson-Edefors,... (6)Undo refine
Do, Minh Quang, ... (6)Undo refine
Drazdziulis, Mindaug ... (2)
University
Chalmers University of Technology (6)
Language
English (6)
Research subject (UKÄ/SCB)
Natural sciences (5)
Engineering and Technology (1)

Year

Kungliga biblioteket hanterar dina personuppgifter i enlighet med EU:s dataskyddsförordning (2018), GDPR. Läs mer om hur det funkar här.
Så här hanterar KB dina uppgifter vid användning av denna tjänst.

 
pil uppåt Close

Copy and save the link in order to return to this view